// ===============================================================================
// FileName : shift_flop.v
// Function : A flip-flop with asynchronous clear, for use in shift register models.
//
// Inherits simulation `timescale.
// -------------------------------------------------------------------------------
//
// Author   : QilinZhao
// Version  : v-1.0
// Date     : 2013-08-29
// E-mail   : forqilin@163.com
// Copyright: QiXin Studio
===============================================================================

module shift_flop (output Q, Qn, input D, Clk, Clr);
  
  reg  QReg;  // Storage
  
  assign #2 Q  =  QReg;  // State changes get own delays.
  assign #1 Qn = ~QReg;
  
  always@(posedge Clk, posedge Clr)
  begin
     if (Clr == 1'b1)
          QReg <= 1'b0;
     else QReg <= D;
   end

endmodule // shift_flop
